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<title>LDDQU—Load Unaligned Integer 128 Bits </title></head>
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<h1>LDDQU—Load Unaligned Integer 128 Bits</h1>
<table>
<tr>
<th>Opcode/Instruction</th>
<th>Op/En</th>
<th>64/32-bit Mode</th>
<th>CPUID Feature Flag</th>
<th>Description</th></tr>
<tr>
<td>
<p>F2 0F F0 /<em>r</em></p>
<p>LDDQU <em>xmm1</em>, <em>mem</em></p></td>
<td>RM</td>
<td>V/V</td>
<td>SSE3</td>
<td>Load unaligned data from <em>mem</em> and return double quadword in <em>xmm1</em>.</td></tr>
<tr>
<td>
<p>VEX.128.F2.0F.WIG F0 /r</p>
<p>VLDDQU xmm1, m128</p></td>
<td>RM</td>
<td>V/V</td>
<td>AVX</td>
<td>Load unaligned packed integer values from mem to xmm1.</td></tr>
<tr>
<td>
<p>VEX.256.F2.0F.WIG F0 /r</p>
<p>VLDDQU ymm1, m256</p></td>
<td>RM</td>
<td>V/V</td>
<td>AVX</td>
<td>Load unaligned packed integer values from mem to ymm1.</td></tr></table>
<h3>Instruction Operand Encoding</h3>
<table>
<tr>
<td>Op/En</td>
<td>Operand 1</td>
<td>Operand 2</td>
<td>Operand 3</td>
<td>Operand 4</td></tr>
<tr>
<td>RM</td>
<td>ModRM:reg (w)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td>
<td>NA</td></tr></table>
<h2>Description</h2>
<p>The instruction is <em>functionally similar </em>to (V)MOVDQU ymm/xmm, m256/m128 for loading from memory. That is: 32/16 bytes of data starting at an address specified by the source memory operand (second operand) are fetched from memory and placed in a destination register (first operand). The source operand need not be aligned on a 32/16-byte boundary. Up to 64/32 bytes may be loaded from memory; this is implementation dependent.</p>
<p>This instruction may improve performance relative to (V)MOVDQU if the source operand crosses a cache line boundary. In situations that require the data loaded by (V)LDDQU be modified and stored to the same location, use (V)MOVDQU or (V)MOVDQA instead of (V)LDDQU. To move a double quadword to or from memory locations that are known to be aligned on 16-byte boundaries, use the (V)MOVDQA instruction.</p>
<h2>Implementation Notes</h2>
<p>In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).</p>
<p>Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.</p>
<h2>Operation</h2>
<p><strong>LDDQU (128-bit Legacy SSE version)</strong></p>
<pre>DEST[127:0] (cid:197) SRC[127:0]
DEST[VLMAX-1:128] (Unmodified)</pre>
<p><strong>VLDDQU (VEX.128 encoded version)</strong></p>
<pre>DEST[127:0] (cid:197) SRC[127:0]
DEST[VLMAX-1:128] (cid:197) 0</pre>
<p><strong>VLDDQU (VEX.256 encoded version)</strong></p>
<pre>DEST[255:0] (cid:197) SRC[255:0]</pre>
<h2>Intel C/C++ Compiler Intrinsic Equivalent</h2>
<p>LDDQU:</p>
<p>__m128i _mm_lddqu_si128 (__m128i * p);</p>
<p>VLDDQU: __m256i _mm256_lddqu_si256 (__m256i * p);</p>
<h2>Numeric Exceptions</h2>
<p>None</p>
<h2>Other Exceptions</h2>
<p>See Exceptions Type 4;</p>
<p>Note treatment of #AC varies.</p></body></html>